Title :
Implementing a high-frequency pattern generator based on combinational merging
Author :
Zukowski, Charles A. ; Bai, Ying-Wen
Author_Institution :
Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
Abstract :
A circuit architecture that can produce a high-frequency digital test pattern by merging a number of low-frequency patterns is implemented. This merging is accomplished using only delay elements and combinational logic, so the circuit´s speed is not limited by clock constraints. Two prototype circuits using transistor-transistor logic (TTL) and emitter-coupled logic (ECL) are presented to demonstrate the approach and to explore implementation issues
Keywords :
combinatorial circuits; delays; emitter-coupled logic; logic testing; transistor-transistor logic; circuit architecture; combinational logic; combinational merging; delay elements; emitter-coupled logic; high-frequency digital test pattern; high-frequency pattern generator; low-frequency patterns; prototype circuits; transistor-transistor logic; Circuit testing; Clocks; Combinational circuits; Delay; Logic; Merging; Multiplexing; Prototypes; Shift registers; Switches;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276202
