Title :
Online testable reversible logic circuit design using NAND blocks
Author :
Vasudevan, D.P. ; Lala, P.K. ; Parkerson, J.P.
Author_Institution :
Dept. of Comput. Sci. & Comput. Eng., Arkansas Univ., Fayetteville, AR, USA
Abstract :
A technique for an on-line testable reversible logic circuit is presented. Three new reversible logic gates have been introduced in this paper. These gates can be used to implement reversible digital circuits of various levels of complexity. The major feature of these gates is that they provide on-line testability for circuits implemented using them. The application of these gates in implementation of a subset of MCNC benchmark circuits is provided.
Keywords :
NAND circuits; circuit complexity; integrated circuit design; integrated circuit testing; logic design; logic gates; logic testing; MCNC benchmark circuit implementation; NAND blocks; circuit complexity; on-line testability; on-line testable reversible logic circuit design; reversible digital circuits; reversible logic gates; Benchmark testing; Circuit testing; Computer science; Digital circuits; Energy dissipation; Logic circuits; Logic devices; Logic gates; Logic testing; Physics computing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
Print_ISBN :
0-7695-2241-6
DOI :
10.1109/DFTVS.2004.1347856
