Title :
Annotated bit flip fault model
Author :
Favalli, Michele
Author_Institution :
DI, Ferrara Univ., Italy
Abstract :
Simulation based fault injection is widely used in order to validate fault tolerant digital circuits with respect to transient faults (TFs). The size of circuits often requires the use of cycle based (accurate) register transfer level (RTL) simulation, which, however, does not account for the timing of the functional units. In this paper, TFs affecting memory elements are annotated by using the timing of the driven combinational logic. Such annotation can be used to increase the accuracy of cycle based RTL fault simulation. This analysis is performed without the need to perform event driven fault simulation, and its results show that relevant errors may be in order in case the IC´s timing is neglected. The accuracy of the proposed technique has been validated by comparing its results with those of event driven simulation.
Keywords :
circuit simulation; combinational circuits; fault simulation; fault tolerance; integrated circuit design; integrated circuit modelling; logic design; logic simulation; timing; IC timing; annotated bit flip fault model; circuit size; cycle based RTL fault simulation; cycle based register transfer level simulation; driven combinational logic timing; event driven fault simulation; fault tolerant digital circuits; functional unit timing; memory elements; relevant errors; simulation based fault injection; transient faults; Analytical models; Circuit faults; Circuit simulation; Digital circuits; Discrete event simulation; Fault tolerance; Logic; Performance analysis; Registers; Timing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
Print_ISBN :
0-7695-2241-6
DOI :
10.1109/DFTVS.2004.1347861
