Some techniques for efficient symbolic simulation-based verification

Some techniques to make symbolic simulation-based verification efficient in practice are presented. The first technique is applied to the verification of nonregular designs. Minimally instantiated symbolic simulation vectors are first generated, and all these vectors are encoded into one vector using auxiliary (parametric) Boolean variables. The second technique also pertains to nonregular designs, and it offers a way to compactly encode input constraints during symbolic simulation. Two variations of this technique are explored. The third technique relates to the verification of regular arrays. It is shown that many regular arrays require input constraints to be obeyed, and that these constraints can be encoded using parametric Boolean variables. Another related technique (applicable to regular arrays where control-flow is data independent) does not encode the input constraints, but takes them into account after symbolic simulation. All the techniques are supported by experimental results