Title :
A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth
Author :
Choi, Youngdon ; Song, Ickhyun ; Park, Mu-Hui ; Chung, Hoeju ; Chang, Sanghoan ; Cho, Beakhyoung ; Kim, Jinyoung ; Oh, Younghoon ; Kwon, Duckmin ; Sunwoo, Jung ; Shin, Junho ; Rho, Yoohwan ; Lee, Changsoo ; Kang, Min Gu ; Lee, Jaeyun ; Kwon, Yongjin ; Kim
Author_Institution :
Samsung Electron., Hwasung, South Korea
Abstract :
Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-NVM, application-oriented approaches using PRAM as main-memory or storage-class memory have been researched [2-3]. These studies suggest that noticeable merits can be achieved by using PRAM in improving power consumption, system cost, etc. However, relatively low chip density and insufficient write bandwidth of PRAMs are obstacles to better system performance. In this paper, we present an 8Gb PRAM with 40MB/s write bandwidth featuring 8Mb sub-array core architecture with 20nm diode-switched PRAM cells [4]. When an external high voltage is applied, the write bandwidth can be extended as high as 133MB/s.
Keywords :
NOR circuits; flash memories; low-power electronics; phase change memories; write-once storage; LPDDR2-NVM; NOR flash; application-oriented approaches; chip density; diode-switched PRAM cells; insufficient write bandwidth; main-memory; memory size 8 GByte; phase-change random access memory; power consumption; program bandwidth; size 20 nm; storage-class memory; sub-array core architecture; system cost; system performance; voltage 1.8 V; Bandwidth; Computer architecture; Phase change random access memory; Resistance; Sensors; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6176872
