• DocumentCode
    166169
  • Title

    ParTejas: A parallel simulator for multicore processors

  • Author

    Malhotra, Geetika ; Aggarwal, Parag ; Sagar, Abhishek ; Sarangi, Smruti R.

  • Author_Institution
    Comput. Sci. Dept., Indian Inst. of Technol., New Delhi, New Delhi, India
  • fYear
    2014
  • fDate
    23-25 March 2014
  • Firstpage
    130
  • Lastpage
    131
  • Abstract
    In this paper, we present the design of a novel multicore simulator called ParTejas. It is a fast shared memory based parallel simulator written in Java. Unlike recently released parallel simulators that mainly rely on sampling, high level models, and highly relaxed synchronization, we primarily rely on novel concurrent data structures. In specific, we use a lock free parallel slot scheduler for synchronizing the accesses of multiple threads at a shared resource, and we use flexible barriers known as phasers to relax synchronization within bounds. We leverage additional language specific features of Java, and demonstrate a mean speedup of 11.8X (simulation speed of 4-8 MIPS) with 64 threads for a suite of Splash2 and Parsec benchmarks.
  • Keywords
    Java; concurrency control; multiprocessing systems; parallel processing; synchronisation; Java language features; ParTejas; accesses synchronization; concurrent data structures; lock free parallel slot scheduler; multicore processors; multicore simulator design; parallel simulator; Computational modeling; Instruction sets; Java; Linux; Multicore processing; Optimization; Pipelines;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on
  • Conference_Location
    Monterey, CA
  • Print_ISBN
    978-1-4799-3604-5
  • Type

    conf

  • DOI
    10.1109/ISPASS.2014.6844470
  • Filename
    6844470