Title :
A 32-core RISC microprocessor with network accelerators, power management and testability features
Author :
Miller, Brian ; Brasili, Derek ; Kiszely, Tim ; Kuhn, Rob ; Mehrotra, Rahul ; Salvi, Manan ; Kulkarni, Mandar ; Varadharajan, Anand ; Yin, Shi-Huang ; Lin, William ; Hughes, Adam ; Stysiack, Bill ; Kandadi, Vasu ; Pragaspathi, Ilan ; Hartman, Dan ; Carlso
Author_Institution :
Cavium, Marlboro, MA, USA
Abstract :
This paper describes our third generation multicore processor that exhibits a high level of integration. The current design doubles the number of cores, triples the frequency and more than quadruples total memory bandwidth over. It contains 700M transistors and has been fabricated in a 65nm process technology, with 10 layers of copper interconnect and C4 bumps. It contains 32 MIPS cores, 4MB of level 2 cache, multiple hardware accelerator units, 4 72b DDR3 memory controllers operating at 1600 MHz, 20 generic SerDes lanes up to 6.25Gb/s, additional network and boot interfaces and general purpose I/Os. Maximum frequency is 1.6GHz for cores and L2 cache. Excluding I/O, thermal design power ranges from 40W to 65W depending on the frequency bin.
Keywords :
cache storage; integrated circuit testing; microprocessor chips; DDR3 memory controller; RISC microprocessor; copper interconnect; frequency 1.66 GHz; frequency 1600 MHz; hardware accelerator unit; level 2 cache; memory size 4 MByte; network accelerator; power 40 W to 65 W; power management; testability feature; third generation multicore processor; transistor; Bandwidth; Cryptography; Hardware; Multicore processing; Program processors; Synchronization; System-on-a-chip;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6176877
