A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier

A low-cost, fully integrated CMOS PA is attractive. The main challenge is to improve its power efficiency. Although many linearization and efficiency improvement techniques have been proposed, most of these techniques are based on feed-forward, which may not be effective under varying PVT and load conditions [1-3]. The bandwidth is the issue for feedback techniques such as Cartesian and polar loop. There is a severe trade-off between output power and bandwidth, since generating high output power requires many gain stages including mixers and multiple drivers, which results in a large group delay. To overcome the trade-off, we propose a PA-closed loop, where an integrated feedback directly controls the final stage of a watt-level CMOS PA, as shown in Fig. 4.6.1. Although stable feedback at RF is difficult, separate phase and amplitude feedback can be realized without the stability issue. Large bandwidth and high output power are simultaneously realized, as the loop contains only the PA in the signal path and it is composed of a small number of building blocks. In addition, the proposed architecture is desirable for system integration, as the PA does not require an off-chip linearizer. The feedback improves ACLR with WCDMA output by 6dB, where the output power and PAE are +27.1dBm and 28%, respectively. Thanks to the feedback nature, it can improve the linearity and efficiency with varying load conditions, and is suitable for the increasing isolator-less applications. The linear output power and PAE are improved by up to 2.3dB and 6%, respectively, while the circuits for the loop consume 28.3mW.