A single latch, high speed double-edge triggered flip-flop (DETFF)

This paper describes an original circuit design of a static CMOS double-edge triggered flip-flop (DETFF). Double. edge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using lower clock frequency (as compared to a circuit with single-edge triggered flip-flops). Therefore, power consumption in DETFF based circuits may be reduced. The proposed flip-flop design has fewer transistors than other published static CMOS DETFFs. The described circuit structure is laid out in a 0.5 μm process. Circuit simulations using Hspice demonstrate that the flip-flop is logically correct and functions as expected. Furthermore, the proposed design rates favorably when compared to existing static CMOS DETFF circuits