DocumentCode
166183
Title
Characterizing the latency hiding ability of GPUs
Author
Shin-Ying Lee ; Wu, Carole-Jean
Author_Institution
Arizona State Univ., Tempe, AZ, USA
fYear
2014
fDate
23-25 March 2014
Firstpage
145
Lastpage
146
Abstract
This paper demonstrates a latency profiling approach to characterize and evaluate for the latency-hiding capability of modern GPU architectures. We find that the fast context-switching and massive multi-threading architecture can effectively hide much of the latency by swapping in and out warps. However, for certain GPGPU applications, such as bfs, the performance is limited by other factors. In future work, we plan to use the latency profiling approach to further investigate the limits of GPUs and seek for performance improvement opportunities.
Keywords
graphics processing units; parallel architectures; performance evaluation; program diagnostics; GPU architectures; context-switching architecture; graphics processing unit architecture; latency hiding ability; latency profiling approach; massive multithreading architecture; Computer architecture; Delays; Graphics processing units; Hazards; Instruction sets; Pipelines; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on
Conference_Location
Monterey, CA
Print_ISBN
978-1-4799-3604-5
Type
conf
DOI
10.1109/ISPASS.2014.6844477
Filename
6844477
Link To Document