New design of squarer circuits using Booth encoding and folding techniques

A new technique is presented for designing a parallel squarer that uses both the Booth encoding and the "traditional" folding technique. The proposed Booth-folding technique achieves a 50% reduction of the number of partial products with respect to the simple folded architecture, allowing a remarkable reduction of propagation delay and power dissipation. In this paper a comparison between two 32-bit squarer circuits, one using the proposed Booth-folding technique and one using the standard folding technique, is presented. Simulation results show that a sensible improvement in area occupation, power dissipation and propagation delay is obtained using the new squarer architecture