Title :
Digital integrated circuit testing for art historians and test experts
Author_Institution :
Stanford Univ., CA, USA
Abstract :
Summary form only given. This paper is an attempt to identify the basic concerns in digital IC production testing. The details, too often, crowd in and prevent us from understanding why we are having difficulties: why testing is too costly or why too many bad chips escape (pass) the test despite our best efforts. Then some of the myths representing the common wisdom about testing are explored. The author´s opinions are supported by the results of experiments - not simulations, but real-world tests - carried out on actual chips from various technologies.
Keywords :
digital integrated circuits; integrated circuit testing; production testing; digital IC production testing; digital integrated circuit testing; Circuit testing; Combinational circuits; Computer science; Digital integrated circuits; Integrated circuit testing; Laboratories; Logic testing; Production; Sequential circuits; Subspace constraints;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on
Print_ISBN :
0-7695-2231-9
DOI :
10.1109/ICCD.2004.1347889