DocumentCode :
166197
Title :
Simulating DRAM controllers for future system architecture exploration
Author :
Hansson, Anders ; Agarwal, Nishant ; Kolli, A. ; Wenisch, Thomas ; Udipi, Aniruddha N.
Author_Institution :
R&D, ARM Ltd., Cambridge, UK
fYear :
2014
fDate :
23-25 March 2014
Firstpage :
201
Lastpage :
210
Abstract :
Compute requirements are increasing rapidly in systems ranging from mobile devices to servers. These, often massively parallel architectures, put increasing requirements on memory bandwidth and latency. The memory system greatly impacts both system performance and power, and it is key to capture the complex behaviour of the DRAM controller when evaluating CPU and GPU performance. By using full-system simulation, the interactions between the system components is captured. However, traditional DRAM controller models focus on modelling interactions between the controller and the DRAM rather than the interactions with the system. Moreover, the DRAM interactions are modelled on a cycle-by-cycle basis, leading to inflexibility and poor simulation performance. In this work, we present a high-level memory controller model, specifically designed for full-system exploration of future system architectures. Our event-based model is tailored to match a contemporary controller architecture, and captures the most important DRAM timing constraints for current and emerging DRAM interfaces, e.g. DDR3, LPDDR3 and WideIO. We show how our controller leverages the open-source gem5 simulation framework, and compare it to a state-of-the-art DRAM controller simulator. Our results show that our model is 7x faster on average, while maintaining the fidelity of the simulation. To highlight the capabilities of our model, we show that it can be used to evaluate a multi-processor memory system.
Keywords :
DRAM chips; logic design; parallel architectures; CPU; DRAM controllers; GPU; LPDDR3; WideIO; contemporary controller architecture; event-based model; full-system exploration; future system architectures; high-level memory controller model; mobile devices; multiprocessor memory system; open-source gem5 simulation framework; parallel architectures; servers; Bandwidth; Computer architecture; Data models; Generators; Random access memory; Switches; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4799-3604-5
Type :
conf
DOI :
10.1109/ISPASS.2014.6844484
Filename :
6844484
Link To Document :
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