DocumentCode
1662041
Title
A FIFO-based architecture for high speed image compression
Author
Masoudnia, A. ; Sarbazi-Azad, H. ; Boussakta, S.
Author_Institution
Sch. of Sci. & Technol., Teeside Univ., Middlesbrough, UK
Volume
1
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
221
Abstract
Proposes a novel architecture for high-performance wavelet-based image compression. Primarily, performance analysis shows that using the normal implementation technology the proposed architecture can process a real-time video stream of up to 35 frames (512×512 pixels) per second
Keywords
VLSI; data compression; parallel architectures; pipeline processing; real-time systems; video coding; wavelet transforms; 262144 pixel; 512 pixel; FIFO-based architecture; VLSI; performance analysis; pipelined architecture; real-time video stream; wavelet-based image compression; Computer architecture; Filters; Frequency; Image coding; Image reconstruction; Spline; Streaming media; Video compression; Wavelet analysis; Wavelet transforms;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN
0-7803-7057-0
Type
conf
DOI
10.1109/ICECS.2001.957720
Filename
957720
Link To Document