DocumentCode
1662100
Title
Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs
Author
Wang, Chua-Chin ; Chiu, Chih-Chiang ; Chien, Yu-Tsung
Author_Institution
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Volume
1
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
233
Abstract
We present two fast half-swing CMOS circuits for NOR-NOR PLA implementation. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced. Besides, the proposed circuit also reveals other advantages of no ground switch, no charge sharing and zero offset
Keywords
CMOS logic circuits; NOR circuits; high-speed integrated circuits; programmable logic arrays; CMOS fast half-swing inter-plane circuit; buffering transmission gate; charge sharing; clocked NOR-NOR PLA; fall delay; ground switch; offset; output response; racing problem; rise delay; voltage source; Clocks; DH-HEMTs; Delay effects; Inverters; Logic gates; Programmable logic arrays; Switches; Switching circuits; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN
0-7803-7057-0
Type
conf
DOI
10.1109/ICECS.2001.957723
Filename
957723
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