Title :
I/O buffer placement methodology for ASICs
Author :
Kozhaya, Joseph N. ; Nassif, Sani R. ; Najm, Farid N.
Author_Institution :
Illinois Univ., Urbana, IL, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
In modern designs, voltage drop on the power grid is becoming a critical concern. One important technique to avoid severe voltage drops is to spread the highly power hungry buffers, such as I/O buffers, around the grid. In this paper, we study the problem of I/O buffer placement in order to avoid hot spots, which are locations on the chip characterized by high voltage drops. The problem is defined mathematically and formulated as an ILP (integer linear programming) problem. Then an efficient greedy heuristic is proposed as an alternative to the expensive ILP solution
Keywords :
algorithm theory; application specific integrated circuits; circuit layout CAD; heuristic programming; integer programming; integrated circuit design; linear programming; logic CAD; ASIC designs; ASICs; I/O buffer placement; I/O buffer placement methodology; I/O buffers; ILP problem; buffers; greedy heuristic algorithm; high voltage drop locations; hot spots; integer linear programming problem; power grid; voltage drop; Application specific integrated circuits; Circuit noise; Delay; Logic circuits; Logic gates; Modems; Noise reduction; Power grids; Robustness; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957726
