Optimised reconfigurable MAC processor architecture

Author

Iliopoulos, M. ; Antonakopoulos, Theodore

Author_Institution

Comput. Technol. Inst. (CTI), Patras, Greece

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

253

Abstract

Inefficient resources utilization is met in various embedded communication devices, which are based on standard processor cores and custom hardware modules. This paper addresses the inefficient resources utilization problem in MAC processor designs and presents a solution that is based on a reconfigurable processor architecture and on dynamic-static instruction partitioning, depending on medium access protocol requirements. The presented instruction partitioning is based on statistical and time critical functional analysis for minimizing the required hardware resources

Keywords

access protocols; circuit optimisation; digital signal processing chips; embedded systems; integrated circuit design; logic partitioning; minimisation; reconfigurable architectures; reduced instruction set computing; statistical analysis; MAC processor design; RISC processor cores; custom hardware modules; dynamic-static instruction partitioning; embedded communication devices; hardware resource minimization; instruction partitioning; medium access control; medium access protocol requirements; optimised reconfigurable MAC processor architecture; resources utilization; standard processor cores; statistical analysis; time critical functional analysis; Access protocols; Computer architecture; Electronic mail; Embedded computing; Energy consumption; Hardware; Media Access Protocol; Process design; Reconfigurable logic; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957728

Filename

957728