The architecture of the LR33020 graphX processor: a MIPS-RISC based X-terminal controller

Author

Desai, Sanjay

Author_Institution

LSI Logic Corp., Milpitas, CA, USA

fYear

1992

Firstpage

205

Lastpage

208

Abstract

The architecture and implementation of a MIPS-RISC-based application-specific microprocessor designed specifically for X-Window terminals is described. It consists of a graphics coprocessor integrated with a MIPS-1 (R3000)-compatible CPU core along with system-level functions found in a typical X-Terminal. The design of the graphics coprocessor has been optimized for accelerating low-level graphics operations typical in X-Windows applications. It is implemented as coprocessor 2. A set of coprocessor 2 graphics instructions process pixel data fetched by dedicated DMA channels through a high-bandwidth (64 b) memory interface. The combination of the graphics coprocessor and high-bandwidth memory interface result in a very high performance. The presence of system-level functions on the same die as the CPU and graphics engine make for a very highly integrated processor

Keywords

computer graphic equipment; microprocessor chips; reduced instruction set computing; LR 33020 graphX processor architecture; MIPS-RISC based X-terminal controller; X-Window terminals; application-specific microprocessor; dedicated DMA channels; high-bandwidth memory interface; low-level graphics; system-level functions; very highly integrated processor; Application specific integrated circuits; Bandwidth; Buffer storage; Control systems; Coprocessors; Displays; Graphics; Hardware; Microprocessors; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-3110-4

Type

conf

DOI

10.1109/ICCD.1992.276249

Filename

276249