Asynchronous scan-latch controller for low area overhead DFT

This paper introduces a new scan control technique to realize low area overhead of scan-latches. Single transparent-latch is popularly used for register of high-throughput datapaths. For the scan-test of those kind of circuits, each transparent-latch is replaced with scan-latch. Conventional scan-latch cells controlled by synchronous signals consist of L1 latch and additional L2 latch, both of which function as master latch and slave latch respectively in scan mode. Apparently, additional L2 latch may result in area overhead. In order to avoid the area impact of such an additional L2 latch, we propose new timing methodology employing asynchronous control technique asP* protocol, and introduce asynchronous controlled scan-paths whose scan-latch employs only L1 latch. We evaluate the operation speed with HSPICE simulations and see they are practical. We also suggest DFT structure with our suggested asynchronous scan-paths, which is suitable for conventional synchronous test systems.