Title :
A new STI-type FinFET device structure for high-performance applications
Author :
Lin, Jyi-Tsong ; Lin, Po-Hsieh ; Eng, Yi-Chuen
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
A new STI-type FinFET structure with its body region been connected is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. From the simulation results, the STI-type FinFET shows that the short-channel effects (SCEs) and the off-state leakage current are proved to be reduced because the threshold voltage (VTH) roll-off and the drain-induced barrier lowering (DIBL) are well controlled. For same reason, this new device also exhibits a higher transconductance (GM) and its GD also maintains a good electrical performance with no kink effect compared with the conventional FinFET. With extra body region under the gate layer, the lattice temperature is decreased, and a good capability of alleviating the thermal instability is also obtained.
Keywords :
MOSFET; leakage currents; numerical analysis; thermal stability; STI-type FinFET device structure; drain-induced barrier lowering; gate layer; lattice temperature; off-state leakage current; short-channel effects; thermal instability; three-dimensional numerical simulations; transconductance; FinFETs; Logic gates; FinFET; STI-type; body-connected region;
Conference_Titel :
Next-Generation Electronics (ISNE), 2010 International Symposium on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4244-6693-1
DOI :
10.1109/ISNE.2010.5669142