A signal integrity test bed for PCB buses

Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circuit design, teams with many designers, long design cycles, and expensive test equipment. By building a "scale model" that operates at bit rates of 50-100 Mbits/sec, we obtain order of magnitude reductions in cost and design time. We present a simple, inexpensive test bed implemented using a PC and inexpensive graphics cards. To demonstrate the effectiveness of our test bed, we use it to validate novel methods for synthesizing crosstalk equalization filters.