Title :
Autonomous-tool for hardware partitioning in a built-in self-test environment
Author :
Chen, Chien-In Henry ; Yuen, Joel ; Lee, Ji-Der
Author_Institution :
Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA
Abstract :
A network partitioning tool, named Autonomous, is presented for partitioning digital combinational portions of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. A built-in self-test (BIST) design generators, named BISTSYN has been developed and implemented to facilitate the BIST design with this partitioning methodology. The experimental results show that Autonomous, when used with BISTSYN on a set of benchmark examples, is feasible for very large designs, and the number of undetected faults is significantly reduced after the circuit is partitioned
Keywords :
built-in self test; combinatorial circuits; logic testing; Autonomous; BISTSYN; benchmark examples; built-in self-test environment; design generators; digital combinational portions; hardware partitioning; network partitioning tool; structural subcircuits; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Hardware; Intelligent networks; Signal design; Signal generators;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276265
