Implementing fair queueing in ATM switches. II. The logarithmic calendar queue

For pt.I see ibid., p.509-18 (1997). The total implementation complexity of cell schedulers which aim at approximating the generalized processor sharing (GPS) policy is the combination of the complexity of their system-potential function and the complexity involved in sorting the timestamps in order to select the cell with minimum timestamp for transmission. Given that several scheduling algorithms which use a system-potential function of O(1) complexity have been introduced (among them, the minimum-delay self-clocked fair queueing (MD-SCFQ) algorithm achieves optimal delay and excellent fairness properties), the major contribution to the total complexity comes from the task of sorting the timestamps every time a cell is transmitted or received, which is common to all GPS-related schedulers. In this paper, we present a technique, called the logarithmic calendar queue (LCQ), that can achieve a dramatic reduction of the implementation complexity of a GPS-related scheduler, at the cost of a very small and controllable degradation of the delay bounds. We then use the LCQ to implement MD-SCFQ with reduced complexity. By applying the general methodology for the delay analysis presented in the first part of this paper (Chiussi et al. 1997), we are able to provide a closed-form expression of the delay bounds as a function of the LCQ design parameters, which can be used to optimize the design. The LCQ is not exclusively related to MD-SCFQ, but can be applied to any GPS-related scheduler to simplify implementation complexity