DocumentCode :
1662681
Title :
A simple process of thin-film transistor using the trench-oxide layer for improving 1T-DRAM performance
Author :
Chiu, Hsien-Nan ; Lin, Jyi-Tsong ; Eng, Yi-Chuen ; Chang, Tzu-Feng ; Chen, Cheng-Hsin
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fYear :
2010
Firstpage :
254
Lastpage :
257
Abstract :
In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (~72%) and the retention time (~50%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.
Keywords :
DRAM chips; isolation technology; thermal stability; thin film transistors; IT-DRAM; TO TFT process; dynamic random access memory; isolation oxide; source-drain tie; thermal stability; thin-film transistor; trench-oxide layer; Logic gates; Random access memory; Substrates; Thin film transistors; 1T-DRAM; TO TFT; source/drain tie;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Next-Generation Electronics (ISNE), 2010 International Symposium on
Conference_Location :
Kaohsiung
Print_ISBN :
978-1-4244-6693-1
Type :
conf
DOI :
10.1109/ISNE.2010.5669149
Filename :
5669149
Link To Document :
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