Efficient multi-node optimal placement for decoupling capacitors on PCB

With the tendency of larger current flow and lower supplied voltage in the modern integrated circuits, the impedance profile of the power distribution network (PDN) should become lower and lower to maintain the power integrity. Selection and placement design of decoupling capacitor becomes critical to achieve a well-designed PDN. Extending single node analysis (SNA), a more efficient method is proposed for multi-node optimization. First, an optimal combination of the decoupling capacitors is presented within a single port region. The optimal result is then applied to all port regions to achieve the desired power integrity. Within the bandwidth of interest, a better PDN design with lower impedance is realized by using fewer decoupling capacitors. Comparing with the commercial tool, Ansys PI advisor, it has the advantage of multi-node optimization and significant reduction of execution times.