Title :
A ratio-independent algorithmic pipeline analog-to-digital converter
Author :
Hatanaka, Shingo ; Taniguchi, Kenji
Author_Institution :
Dept. of Electron. & Inf. Syst., Osaka Univ., Japan
fDate :
6/23/1905 12:00:00 AM
Abstract :
Since mismatch of ratio capacitors used in pipeline ADC limits the performance of high resolution ADCs, we introduced a new algorithm to alleviate mismatch of capacitors in which signal and reference voltages are sampled using the same capacitor though 4 clock phases. The design for 14 bit, 10 Msample/s CMOS pipelined ADC using 3 V supply voltage and 0.35 μm CMOS process is described
Keywords :
CMOS integrated circuits; analogue-digital conversion; pipeline processing; 0.35 micron; 14 bit; 3 V; CMOS pipeline analog-to-digital converter; capacitor mismatch; ratio-independent algorithm; Analog-digital conversion; CMOS process; Capacitors; Circuits; Clocks; Information systems; Operational amplifiers; Pipelines; Signal resolution; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957750
