Title :
A novel CMOS charge-pump circuit with positive feedback for PLL applications
Author :
Juárez-Hernández, Esdras ; Díaz-Sánchez, Alejandro
Author_Institution :
Nat. Inst. for Astrophysics, Opt. & Electron., Puebla, Mexico
fDate :
6/23/1905 12:00:00 AM
Abstract :
The design and simulation of a novel CMOS charge-pump circuit for PLL applications is presented. The proposed circuit makes use of positive feedback to increase the switching speed and current reuse to minimize the power consumption. H-SPICE simulations for a 0.35 μm AMS technology show the potential of the proposed structure for high-frequency applications
Keywords :
CMOS analogue integrated circuits; circuit feedback; phase locked loops; 0.35 micron; AMS technology; CMOS charge-pump circuit; H-SPICE simulations; PLL applications; current reuse; high-frequency applications; positive feedback; power consumption minimisation; switching speed; Charge pumps; Circuit simulation; Energy consumption; Feedback circuits; Optical feedback; Phase frequency detector; Phase locked loops; Switches; Switching circuits; Voltage-controlled oscillators;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957751
