Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process

Author

Ker, Ming-Dou ; Chuang, Che-Hao ; Lo, Wen-Yu

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Taiwan

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

361

Abstract

The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18- μm salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more compactly, but is still able to provide deep-submicron CMOS ICs with higher ESD robustness

Keywords

CMOS analogue integrated circuits; MOSFET; VLSI; current distribution; electrostatic discharge; integrated circuit layout; integrated circuit reliability; 0.18 micron; ESD robustness; I/O cell; deep-submicron CMOS; layout design; multi-finger MOSFET devices; salicided CMOS process; uniform ESD current distribution; CMOS integrated circuits; CMOS process; CMOS technology; Electrostatic discharge; Fingers; Integrated circuit layout; MOS devices; MOSFET circuits; Protection; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957754

Filename

957754