Title :
Sequential circuit design using synthesis and optimization
Author :
Sentovich, E.M. ; Singh, Kanwar Jit ; Moon, Cho ; Savoj, Hamid ; Brayton, Robert K. ; Sangiovanni-Vincentelli, Alberto
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits
Keywords :
logic design; optimisation; sequential circuits; MISII; SIS; interactive tool; logic-level description; optimization; optimized net-list; sequential circuit design; sequential input-output behavior; state transition table; synthesis; Circuit synthesis; Clocks; Design optimization; Encoding; Logic circuits; Optimized production technology; Registers; Sequential circuits; Testing; Timing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-3110-4
DOI :
10.1109/ICCD.1992.276282