Implementation and bandwidth considerations in multi ported, on chip data cache

As CPU workload increases, the on-chip cache becomes a bottleneck for data transfer. In this paper, we evaluate the cache efficiency in terms of data bandwidth (BW), or the number of data accesses per cycle that a cache can handle. Four cache configurations are described and tested for the best BW performance. This paper deals not only with the type of two-level cache configuration but also with the best size ratios of the two levels. The results given are based on tests conducted with a cache simulation supporting two-level cache configurations