A low power dual-mode pulse triggered flip-flop using pass transistor logic

In this paper, a novel dual-mode pulse-triggered FF design supporting functional versatility is presented. A dual-mode pulse generator design in pass transistor logic (PTL) is devised first. The threshold voltage loss problem common in PTL design is successfully resolved while the circuit simplicity is kept. By combining the pulse generator with a level sensitive latch, a dual-mode pulse-triggered flip-flop (DMP-FF) design is derived. Extensive performance comparisons against various single mode FF designs are conducted. The proposed design, bearing similar circuit complexity plus the advantage of dual mode operations, performs equally well as single mode counterparts in various AC parameters and power consumption.