Cycle efficient bit rate matching for LTE-a with insructions support

Efficient software implementation of Long Term Evolution Advanced (LTE-A) wireless standard over word-based micro-processor architecture is investigated. The very high data rate of LTE-A requires more sophisticated and high throughput bit level algorithms. Due to data format mismatch, traditional word-based microprocessors face great challenge implementing these complex bit-manipulations. In this work, the implementation of bit-level interleaving operation using perfect shuffling word-level instruction is studied. In particular, an efficient implementation of bit-rate matching algorithm is demonstrated on the Texas Instruments c6416 CCS cycle accurate simulator with order of magnitude performance enhancement.