DocumentCode
1663240
Title
An area minimizer for floorplans with L-shaped regions
Author
Sun, Yachyang ; Liu, C.L.
Author_Institution
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
fYear
1992
Firstpage
383
Lastpage
386
Abstract
Given a floorplan with L-shaped regions, the problem considered is to choose an implementation from a set of possible implementations for each module such that the resultant floorplan will have minimum area, subject to the constraint that the dual polar graphs of the floorplan must be preserved. The concept of a cut line is extended, and eight types of cut lines that are used to decompose floorplans with L-shaped regions are defined. An O (n 3) time algorithm for deciding whether a given floorplan is decomposable is presented. A heuristic algorithm, which uses the cut tree obtained by the decomposition algorithm to solve the area minimization problem, is proposed. For floorplans that can not be decomposed by the decomposition algorithm, a branch-and-bound algorithm can be incorporated into the algorithm to solve the area minimization problem. The results obtained are superior to those obtained by running an existing mathematical programming package for at least 1 h, and the execution time is less than 3 min for the most complex test problem
Keywords
VLSI; circuit layout CAD; mathematical programming; L-shaped regions; VLSI; area minimizer; branch-and-bound algorithm; cut line; decomposition algorithm; dual polar graphs; floorplans; heuristic algorithm; mathematical programming package; Algorithm design and analysis; Heuristic algorithms; Mathematical programming; Minimization methods; Packaging; Polynomials; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-3110-4
Type
conf
DOI
10.1109/ICCD.1992.276295
Filename
276295
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