Cache array architecture optimization at deep submicron technologies

A cache access time model, PRACTICS (predictor of access and cycle time for cache stack), has been developed to optimize the memory array architecture for the minimum access and cycle times of on-chip memory using circuit models based on Cadence simulations. Lumped RC models have been used to approximate the distributed RC interconnect network in the access time models. Both SRAM and DRAM models have been validated with industrial designs. The limited influences of gate far-out and transistor size on the cache array architecture indicate that interconnect delay is dominant at deep submicron technologies.