An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface

In high-speed wireline communication, full-rate clocking for chip-to-chip interface has been widely adopted since it eliminates clock-induced deterministic jitter. Design with standard digital CMOS technologies, however, often limits the maximum frequency of circuit operation. The increase in power and circuit complexity in full-rate clocking makes the problem even worse in the design of a parallel transceiver whose clock tree travels through long interconnects. As an alternative to the full-rate clocking, frequency generation with a multiphase PLL has been also considered to relax the tight requirements of operating frequency of oscillator and flip-flops. DRAM interface, as a representative of high-speed parallel links, has adopted quadruple data rate (QDR) schemes for high-speed graphic applications [1-2]. However, as the data rate of DRAM interface increases up to multi-Gb/s range, skew in quadrature clock phases presents one of the most serious performance degradation factors.