Title :
A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link
Author :
Amirkhany, Amir ; Kaviani, Kambiz ; Abbasfar, Aliazam ; Shuaeb, Fazeel ; Beyene, Wendem ; Hoshino, Chikara ; Madden, Chris ; Chang, Ken ; Yuan, Chuck
Author_Institution :
Rambus, Sunnyvale, CA, USA
Abstract :
This paper introduces coded differential (CD) signaling for high-speed parallel electrical links. CD preserves the desirable properties of differential signaling while offering ISI mitigation that is superior to 1-tap decision feedback equalization (DFE) [1-2] at no loss in pin efficiency or throughput. Specifically, CD encodes two bits of data over four binary wires in such a way that post-cursor inter-symbol interference (ISI) is completely eliminated across the entire unit-interval (UI). CD signaling is NRZ on individual wires and is balanced across the bus, meaning over any UI half the four-wire set have a high signaling level while the other half have a low level. The balanced nature of signaling leads to low supply switching noise. Received data is detected differentially by discriminating the difference between the signals on wire pairs without the need for a fixed reference voltage.
Keywords :
decision feedback equalisers; interference suppression; intersymbol interference; 1-tap decision feedback equalization; CD signaling; ISI mitigation; NRZ; UI; bit rate 16 Gbit/s; coded differential bidirectional parallel electrical link; coded differential signaling; four-wire set; high-speed parallel electrical links; low supply switching noise; post-cursor intersymbol interference; unit-interval; Clocks; Decoding; Latches; Multiplexing; Prototypes; Receivers; Wires;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6176953