Title :
On the design of modulo 2n±1 adders
Author :
Efstathiou, C. ; Vergos, H.T. ; Nikolos, D.
Author_Institution :
Dept. of Informatics, TEI of Athens, Greece
fDate :
6/23/1905 12:00:00 AM
Abstract :
In this paper we present new architectures for the design of modulo 2n±1 adders, which are based on the use of the same design block. Our design block incorporates a parallel-prefix carry computation unit with a carry increment stage. VLSI implementations of the proposed architectures in a static CMOS technology reveal their superiority against all already known architectures when the area * time 2 product is used as a metric and n > 8
Keywords :
CMOS digital integrated circuits; VLSI; adders; carry logic; integrated circuit design; parallel architectures; VLSI architectures; carry increment stage; carry-increment adders; design block; modulo 2n±1 adders; parallel-prefix carry computation unit; short execution times; static CMOS technology; Algorithm design and analysis; Computer architecture; Concurrent computing; Costs; Delay; Logic; Tin; Tree data structures;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957792
