Characterisation of new vertical MOSFETs with recessed gate

This study presents a new vertical MOSFET with recessed gate (RG). Based on the TCAD simulation results, our proposed VMOS structure can gain reduced parasitic capacitance (compared to the conventional VMOS, both C_gd and C_gs can be reduced about 12% and 38.78%, respectively at V_Ds =1.0 V), improved drain saturation current, and free kink characteristics, in comparison to a conventional VMOS structure. Moreover, the short-channel characteristics of RGVMOS which is modified from the EGVMOS are still acceptable. Most importantly, the manipulation of fabricating this newly proposed structure is enhanced mainly owing to the semicircle gate scheme.