Distributed arithmetic radix-2 butterflies for FPGA

This paper systematizes the design of radix-2 DIF butterflies for large FFTs based on distributed arithmetic. The butterflies are suitable for FFTs up to 4096 points and have been efficiently mapped on FPGA. Two improvements have been proposed with respect the previously published structures. First, the use of 5-input LUTs allows codifying higher number of angles per stage and does not reduce the throughput. Second, minimum area butterflies are obtained by combining the three methods explained in the paper. In such a case, the performance is increased: the area and the latency are reduced and the throughput is increased