A divider-multiplier high level synthesis library element for DSP applications

Author

Rodellar, V. ; Sacristan, M.A. ; Alvarez, A. ; Diaz, A. ; Peinado, V. ; Gómez, P.

Author_Institution

Fac. de Inf., Univ. Politecnica de Madrid, Spain

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

547

Abstract

In this paper a divider-multiplier reusable library cell is presented. The division is implemented by means of an algorithm based on successive multiplications. The resulting structure uses a fixed-point format and two´s complement arithmetic for operands of any size. It is coded with the VHDL synthetizable subset for the Synopsys^TM Behavioral Compiler. The performance results in terms of area and time delay for different operand sizes and technologies are presented and discussed

Keywords

dividing circuits; field programmable gate arrays; fixed point arithmetic; hardware description languages; high level synthesis; multiplying circuits; signal processing; software reusability; DSP applications; SynopSyS Behavioral Compiler; VHDL synthetizable subset; digital signal processing; divider-multiplier high level synthesis library element; divider-multiplier reusable library cell; fixed-point format; operand sizes; successive multiplications; two´s complement arithmetic; Algorithm design and analysis; Circuits; Delay effects; Digital signal processing; Fixed-point arithmetic; High level synthesis; Libraries; Signal design; Signal processing algorithms; Software prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957801

Filename

957801