Design and implementation of scalable low-power Montgomery multiplier

In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects are considered: performance, power, reliability, and scalability. To increase performance, the architecture is based on the radix-4 carry-save adder (CSA). To lower power consumption, we devised several effective techniques for reducing the spurious transitions and the expected switching activity (ESA) of high fan-out signals. To achieve scalability, we implement a 4-fold nested loop for the whole data processing flow. It is compatible with the multiple-precision digit-serial arithmetic as well as the data transfer to/from an external memory. Finally, to make sure that the arithmetic operation runs correctly without inducing data overflow error, we find out the optimum numbers of bits for all vectors appearing in the operation through a mathematical analysis and a logic simulation. In the evaluation of hardware implemented using 0.18 μm CMOS standard library and 4 metal layers, area and current consumption are 59 K gates and 0.4 mA/MHz at 1.8 V supply voltage, respectively. The presented low power techniques save more than 20% of power consumed.