• DocumentCode
    1664856
  • Title

    An improved self-reconfigurable interconnection scheme for a Coarse Grain Reconfigurable Architecture

  • Author

    Shami, Muhammad Ali ; Hemani, Ahmed

  • Author_Institution
    Sch. of ICT, R. Inst. of Technol., KTH, Stockholm, Sweden
  • fYear
    2010
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    An improved Dynamic, Partial and self reconfigurable interconnection network (Hybrid-2 Network) is presented for Dynamically Reprogrammable Resource Array (DRRA), which is a Coarse Grain Reconfiguration Architecture (CGRA). To justify the design decision, Hybrid-2 network implementation is compared against the possible implementations using Multiplexer, NoC, Crossbar and already published Hybrid-1 interconnection network. Results shows that newly presented Hybrid-2 Interconnection network take (1.08x, 0.104x, 0.212x and 0.681x) the area, (1x, 0.037x, 0.026x and 0.107x) the configuration bits of Multiplexer, NoC, Crossbar and Hybrid-1 Implementation respectively. Hybrid-2 network is also 2.87x and 5.86x faster than Multiplexer and Hybrid-1 networks.
  • Keywords
    multiprocessor interconnection networks; network-on-chip; reconfigurable architectures; Hybrid-1 interconnection network; Hybrid-2 Interconnection network; NoC; coarse grain reconfigurable architecture; dynamically reprogrammable resource array; improved self reconfigurable interconnection scheme; multiplexer; network-on-chip; Delay; Fabrics; Integrated circuit interconnections; Multiplexing; Multiprocessor interconnection; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    NORCHIP, 2010
  • Conference_Location
    Tampere
  • Print_ISBN
    978-1-4244-8972-5
  • Electronic_ISBN
    978-1-4244-8971-8
  • Type

    conf

  • DOI
    10.1109/NORCHIP.2010.5669436
  • Filename
    5669436