Title :
A low-power, medium-resolution, high-speed CMOS pipelined ADC
Author :
Meganathan, D. ; Jantsch, Axel
Author_Institution :
Dept. of Electron. Eng., Anna Univ., Chennai, India
Abstract :
This paper presents the systematic design approach of a low-power, medium-resolution, high-speed pipelined Analog-to-Digital Converter (ADC). The ADC is implemented in 180nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB, spurious-free dynamic range of 89 dB and effective number of bits of 9.64-bits at sampling speed of 50MHz with an input signal frequency of 4MHz. The peak differential-nonlinearity of the converter is 0.28/-0.17LSB and integral-nonlinearity of the converter is +0.42/-0.41LSB. The proposed 10-bit, 50MS/sec pipelined ADC consumes 24.5mW amount of power from 1.8V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; low-power electronics; analog-to-digital converter; differential nonlinearity; digital CMOS technology; high-speed CMOS pipelined ADC; integral nonlinearity; low-power CMOS pipelined ADC; medium-resolution CMOS pipelined ADC; signal-to-noise distortion ratio; CMOS integrated circuits; Capacitors; Converters; Dynamic range; Pipelines; Switches; Switching circuits; Analog-to-digital Sub Converter (ADSC); Dynamic Range (DR); Multiplying Digital-to-Analog Converter (MDAC); Operational Transconductance Amplifier (OTA); Signal-to-noise distortion ratio (SNDR); Spurious Free Dynamic Range (SFDR);
Conference_Titel :
NORCHIP, 2010
Conference_Location :
Tampere
Print_ISBN :
978-1-4244-8972-5
Electronic_ISBN :
978-1-4244-8971-8
DOI :
10.1109/NORCHIP.2010.5669438
