Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM

High-performance microprocessors and SoCs include multiple embedded memory arrays used as register files and low-level caches that typically share the same supply voltage as the core. The desire for wide voltage range operation to optimize power and performance dictates the need for SRAM arrays that can achieve both high performance and low minimum voltage of operation (V_MIN). The 8T bitcell is commonly used in these applications because its decoupled read and write ports offer fast read (RD) and write (WR) operations with generally lower V_MIN than the 6T bitcell. However, process variations result in mismatches between the pull-up and access devices limiting write V_MIN, and/or between read port and keeper transistors limiting read V_MIN. Traditional device up-sizing provides diminishing returns at a large area and power cost. In addition to cell upsizing, dynamic assist techniques have been used for V_MIN reduction in 6T and 8T arrays - examples include temporary collapse of bitcell voltage for write V_MIN reduction and boosting read and write wordlines requiring careful design of the embedded charge pump and the level shifters. In contrast, this paper describes a new capacitive-coupling (CC) write wordline boost which employs intrinsic coupling capacitance between write bitlines (WBL) and accessed write wordline (WWL) to boost WWL without the need for a charge pump or complex level shifters. The scheme has a built-in self-induced V_CC collapse (SIC) allowing the cell voltage to partially collapse during the write operation, further improving write V_MIN. The technique is implemented in a 12KB, 8T cell macro with cell area of 0.238μm², fabricated in a 22nm CMOS technology.