Title :
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC
Author :
Elshazly, Amr ; Inti, Rajesh ; Young, Brian ; Hanumolu, Pavan Kumar
Author_Institution :
Oregon State Univ., Corvallis, OR, USA
Abstract :
Highly digital clock generator architectures, most commonly implemented using digital phase-locked loops (DPLLs), are evolving as the preferred means for synthesizing on-chip clocks. Their main benefits include small area, reduced sensitivity to analog circuit imperfections, and easier scalability to newer processes. However, conflicting bandwidth requirements to simultaneously suppress TDC quantization error and oscillator phase noise poses several design challenges.
Keywords :
circuit noise; clocks; jitter; phase locked loops; DPLL; TDC quantization error; analog circuit; digital MDLL; digital clock generator architectures; digital phase-locked loops; frequency 1.5 GHz; integrated jitter; on-chip clocks; oscillator phase noise; power 890 muW; Bandwidth; Clocks; Jitter; Phase locked loops; Phase noise;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6176993
