A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, −55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC

Highly digital clock generator architectures, most commonly implemented using digital phase-locked loops (DPLLs), are evolving as the preferred means for synthesizing on-chip clocks. Their main benefits include small area, reduced sensitivity to analog circuit imperfections, and easier scalability to newer processes. However, conflicting bandwidth requirements to simultaneously suppress TDC quantization error and oscillator phase noise poses several design challenges.