Title :
A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS
Author :
Hsieh, Min-Han ; Chen, Liang-Hsin ; Liu, Shen-Iuan ; Chen, Charlie Chung-Ping
Author_Institution :
Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Delay-locked loops (DLLs) are widely adopted for clock generation and synchronization in high performance digital systems. The design of analog DLLs has become a challenge due to the trends associated with CMOS scaling, namely, high leakage current, low supply voltage, etc. Consequently, many designers have shifted their focus to digitally-assisted or all-digitally implemented DLLs, which are easier to design for wide range and fast-locking requirements. Due to the need for wide operating frequency range applications in all-digital DLLs (ADDLLs), many delay cells are normally deployed. As a result, a large portion of the die area is consumed by the delay cells. To address this issue, we develop a phase-tracing delay unit (PTDU) technique to reduce delay-cell usage and achieve low area and low power. In this paper, a 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking ADDLL based on the PTDU method is realized in 90nm CMOS technology.
Keywords :
CMOS integrated circuits; delay lock loops; synchronisation; CMOS technology; clock generation; clock synchronization; delay cells; delay-locked loops; fast-locking all-digital DLL; frequency 6.7 MHz to 1.24 GHz; phase-tracing delay unit; size 90 nm; CMOS integrated circuits; Clocks; Delay; Logic gates; Registers; Solid state circuits;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-0376-7
DOI :
10.1109/ISSCC.2012.6176994
