Design of CMOS sampling switch for ultra-low power ADCs in biomedical applications

This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakage-reduction has been designed for a 10-bit 1-kS/s successive approximation (SA) ADC in a standard 130 nm CMOS process. Post-layout simulation shows that the ADC with the proposed switch offers an effective number of bits (ENOB) of 9.5 while consuming only 64 nW.