A programmable and highly pipelined PPP architecture for Gigabit IP over SDH/SONET

This paper details the implementation of a highly pipelined 2.5 Gbit/s point-to-point-protocol packet processor (P⁵) aimed at the latest system-on-a-programmable-chip (SoPC) technology. Throughput rates beyond 2.5 Gbit/s based on FPGA technology could be achieved by designing a new highly pipelined and parallel processing architecture for frames and datagrams. A novel pipelined data sorting mechanism with an extremely low resynchronization buffer and backpressure scheme are introduced to keep the data memory requirements as low as possible for embedded on-chip applications.