A programmable and highly pipelined PPP architecture for Gigabit IP over SDH/SONET

Author

Toal, Ciaran ; Sezer, Sakir

Author_Institution

Sch. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK

fYear

2003

Abstract

This paper details the implementation of a highly pipelined 2.5 Gbit/s point-to-point-protocol packet processor (P⁵) aimed at the latest system-on-a-programmable-chip (SoPC) technology. Throughput rates beyond 2.5 Gbit/s based on FPGA technology could be achieved by designing a new highly pipelined and parallel processing architecture for frames and datagrams. A novel pipelined data sorting mechanism with an extremely low resynchronization buffer and backpressure scheme are introduced to keep the data memory requirements as low as possible for embedded on-chip applications.

Keywords

Internet; SONET; embedded systems; field programmable gate arrays; parallel architectures; pipeline processing; protocols; synchronous digital hierarchy; system-on-chip; 2.5 Gbit/s; FPGA technology; Gigabit IP; Internet; SDH/SONET; SoPC; backpressure scheme; data sorting mechanism; datagrams; embedded on-chip applications; frames; parallel processing architecture; pipelined PPP architecture; point-to-point-protocol packet processor; programmable PPP architecture; resynchronization buffer; system-on-a-programmable-chip; Buildings; Internet; Parallel processing; Payloads; Protocols; SONET; Synchronous digital hierarchy; Telecommunication traffic; Throughput; Videoconference;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing Symposium, 2003. Proceedings. International

ISSN

1530-2075

Print_ISBN

0-7695-1926-1

Type

conf

DOI

10.1109/IPDPS.2003.1213331

Filename

1213331