A scalable, non-interfering, synthesizable Network-on-chip monitor

Today´s Multi-Processor System-on-Chips incorporate advanced communication mechanisms, called Network-on-Chip, to interconnect multiple resources such as processors, memories and accelerators. The detailed evaluation of these communication networks calls for low-level tools that allow detailed performance analysis at the level of the network instead of the analysis at the Processing Elements. We present a freely available toolset to perform such analysis. First level of data analysis is done on HW level on FPGA. 100Mbit/s ethernet connection is used to collect the data to host PC to be further processed and analyzed using a simple and intuitive graphical interface. Finally, we show a case study of an evaluation of an MPEG-4 encoder utilizing the NoC paradigm. We were able to compare link utilizations, stall cycles, and system performance by any time window from 500 clock cycles to the whole running time of 5 seconds at 25 MHz. The system needed to run only once, producing 43 MB of binary data with 250 000 data points, each presenting statistics for every link in the network. The total HW area overhead for monitoring was 4.8%.