• DocumentCode
    1665146
  • Title

    Analysis of modeling styles on Network-on-Chip simulation

  • Author

    Lehtonen, Lasse ; Salminen, Erno ; Hämäläinen, Timo D.

  • Author_Institution
    Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere, Finland
  • fYear
    2010
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    This paper analyses the effects of Network-on-Chip (NoC) models written in SystemC on simulation speed. Two Register Transfer Level (RTL) models and Approximately Timed (AT) and Loosely Timed (LT) Transaction Level (TL) models are compared against reference RTL VHDL 2D mesh model. Three different mesh sizes are evaluated using a commercial simulator and OSCI SystemC reference kernel. Studied AT model achieved 13-40× speedup with modest 10% estimation error.
  • Keywords
    electronic engineering computing; logic design; network-on-chip; NoC; OSCI SystemC reference kernel; RTL model; approximately timed transaction level; loosely timed transaction level; network-on-chip simulation; register transfer level; Analytical models; Computational modeling; Estimation error; Kernel; Load modeling; Time domain analysis; Time varying systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    NORCHIP, 2010
  • Conference_Location
    Tampere
  • Print_ISBN
    978-1-4244-8972-5
  • Electronic_ISBN
    978-1-4244-8971-8
  • Type

    conf

  • DOI
    10.1109/NORCHIP.2010.5669448
  • Filename
    5669448
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1665146